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AD8348
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
LOIP 1
28 LOIN
VPOS1 2
IOPN 3
IOPP 4
VCMO 5
IAIN 6
COM3 7
IMXO 8
COM2 9
IFIN 10
IFIP 11
VPOS2 12
IOFS 13
VREF 14
AD8348
TOP VIEW
(Not to Scale)
27 COM1
26 QOPN
25 QOPP
24 ENVG
23 QAIN
22 COM3
21 QMXO
20 VPOS3
19 MXIN
18 MXIP
17 VGIN
16 QOFS
15 ENBL
Figure 2. 28-Lead TSSOP Pin Configuration
Table 3. Pin Function Descriptions—28-Lead TSSOP
Equivalent
Pin No.
1, 28
Mnemonic
LOIP, LOIN
Description
LO Inputs. For optimum performance, these inputs should be ac-coupled and driven
Circuit
A
differentially. Differential drive from single-ended sources can be achieved via a balun.
To obtain a broadband 50 Ω input impedance, connect a 60.4 Ω shunt resistor between
LOIP and LOIN. Typical input drive level is equal to ?10 dBm.
2, 12, 20
VPOS1, VPOS2,
VPOS3
Positive Supply for LO, IF, and Biasing and Baseband Sections, Respectively. These pins
should be decoupled with 0.1 μF and 100 pF capacitors.
3, 4, 25, 26
5
IOPN, IOPP,
QOPP, QOPN
VCMO
I- and Q-Channel Differential Baseband Outputs. Typical output swing is equal to 2 V p-p
differential. The dc common-mode voltage level on these pins is set by the voltage on VCMO.
Baseband DC Common-Mode Voltage. The voltage applied to this pin sets the dc
B
C
common-mode levels for all the baseband outputs and inputs (IMXO, QMXO, IOPP, IOPN,
QOPP, QOPN, IAIN, and QAIN). This pin can be connected either to VREF or to a reference
voltage from another device (typically an ADC).
6, 23
IAIN, QAIN
I- and Q-Channel Baseband Amplifier Inputs. The single-ended signals on these pins are
D
referenced to VCMO and must have a dc bias equal to the dc voltage on the VCMO pin. If
IMXO (QMXO) is dc-coupled to IAIN (QAIN), biasing will be provided by IMXO (QMXO). If
an ac-coupled filter is placed between IMXO and IAIN, these pins can be biased from the
source driving VCMO through a 1 kΩ resistor. The gain from IAIN/QAIN to the differential
outputs (IOPP/IOPN and QOPP/QOPN) is 20 dB.
7, 22
COM3
Ground for Biasing and Baseband Sections.
8, 21
IMXO, QMXO
I- and Q-Channel Mixer Baseband Outputs. These are low impedance (40 Ω) outputs whose
H
bias levels are set by the voltage applied to the VCMO pin. These pins are typically connected
to IAIN and QAIN, respectively, either directly or through a filter. Each output can drive a
maximum current of 2.5 mA.
9
COM2
IF Section Ground.
10, 11
IFIN, IFIP
IF Inputs. IFIN should be ac-coupled to ground. The single-ended IF input signal should
E
be ac-coupled into IFIP. The nominal differential input impedance of these pins is 200 Ω.
For a broadband 50 Ω input impedance, a minimum-loss L pad should be used; R SERIES = 174 Ω,
R SHUNT = 57.6 Ω. This provides a 200 Ω source impedance to the IF input. However, the AD8348
does not necessarily require a 200 Ω source impedance, and a single shunt 66.7 Ω resistor
can be placed between IFIP and IFIN.
13, 16
IOFS, QOFS
I- and Q-Channel Offset Nulling Inputs. DC offsets on the I-channel mixer output (IMXO)
F
can be nulled by connecting a 0.1 μF capacitor from IOFS to ground. Driving IOFS with a
fixed voltage (typically a DAC calibrated such that the offset at IOPP/IOPN is nulled) can
extend the operating frequency range to include dc. The QOFS pin can likewise be used
to null offsets on the Q-channel mixer output (QMXO).
14
VREF
Reference Voltage Output. This output voltage (1 V) is the main bias level for the device
G
and can be used to externally bias the inputs and outputs of the baseband amplifiers.
The typical maximum drive current for this output is 2 mA.
Rev. A | Page 7 of 28
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